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asahi kasei [AK4117] ms0157-e-03 2004/04 - 1 - general description the AK4117 is a s/pdif aes/ebu receiver supporting sample rates up to 192khz and resolution up to 24-bit. the integrated channel status decoder supports both consumer and professional modes. the AK4117 can automatically detect a non-pcm bit stream. combining the AK4117 with a multi-channel codec such as akm?s ak4527b or ak4529 can create a complete ac-3 system. mode settings can be controlled via microprocessor serial interface. a low power mode is available for normal speed modes and the small 24pin vsop package saves board space. *ac-3 is a trademark of dolby laboratories. features ? aes3, iec60958, s/pdif, eiaj cp1201 compatible ? low jitter analog pll ? pll lock range : 32khz to 192khz ? clock source: pll or x'tal ? 2-channel receiver inputs selector ? auxiliary digital input ? detection functions - non-pcm bit stream detection - dts-cd bit stream detection - sampling frequency detection (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176.4khz, 192khz) - unlock & parity error detection - validity flag detection ? up to 24bit audio data format ? audio i/f: left justified, right justified (16bit, 18bit, 20bit, 24bit), i 2 s ? 40-bit channel status buffer ? burst preamble bit pc and pd buffer for non-pcm bit stream ? q-subcode buffer for cd bit stream ? 4-wire serial p i/f ? master clock output: 128fs/256fs/512fs ? operating voltage: 2.7 to 3.6v ? small package: 24pin vsop ? ta: -40 to 85 c low power 192khz digital audio receive r AK4117
asahi kasei [AK4117] ms0157-e-03 2004/04 - 2 - ? block diagram input selector clock recovery clock generator daif decoder ac-3/mpeg detect p i/f audio i/f x'tal oscillator pdn int0 lrck bick sdto daux xto xti r avdd avss cdti cdto cclk csn dvdd dvss mcko rx0 rx1 error & detect status int1 q-subcode buffer 2 to 1 uout
asahi kasei [AK4117] ms0157-e-03 2004/04 - 3 - ? ordering guide AK4117vf -40 ~ +85 c 24pin vsop (0.65mm pitch) ? pin layout 6 5 4 3 2 1 r avdd nc rx1 rx0 dvdd dvss 7 xti 8 avss pdn int0 int1 csn cclk cdti cdto top view 10 9 xto lrck bick 11 sdto 12 uout nc mcko daux 19 20 21 22 23 24 18 17 15 16 14 13
asahi kasei [AK4117] ms0157-e-03 2004/04 - 4 - pin/function no. pin name i/o function 1 r - external resistor pin 12k ? -5% ~ 13k ? +5% resistor to avss externally. 2 avdd - analog power supply pin 3 rx1 i receiver channel 1 (internal biased pin) 4 nc - no connect no internal bonding. 5 rx0 i receiver channel 0 (internal biased pin) 6 dvdd - digital power supply pin 7 dvss - digital ground pin 8 xti i x'tal input pin 9 xto o x'tal output pin 10 lrck o output channel clock pin 11 bick o audio serial data clock pin 12 sdto o audio seri al data output pin 13 daux i auxiliary audio data input pin 14 mcko o master clock output pin 15 nc - no connect no internal bonding. 16 uout o u-bit output pin when uoute bit = ?0?, uout pin = ?l?. 17 cdto o control data output pin 18 cdti i control data input pin 19 cclk i control data clock pin 20 csn i chip select pin 21 int1 o interrupt 1 pin 22 int0 o interrupt 0 pin 23 pdn i power-down & reset pin when ?l?, the AK4117 is powered-down and reset, and all output pins go to ?l? and the control registers are reset to default state. 24 avss - analog ground pin note 1: all input pins except internal biased pins should not be left floating.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 5 - absolute maximum ratings (avss, dvss=0v; note 2) parameter symbol min max units power supplies: analog digital |avss-dvss| (note 3) avdd dvdd ? gnd -0.3 -0.3 4.6 4.6 0.3 v v v input current (any pins except supplies) iin - 10 ma input voltage (except rx0, rx1 pins) (rx0, rx1 pins) vin1 vin2 -0.3 -0.3 dvdd+0.3 avdd+0.3 v v ambient temperature (power applied) ta -40 85 c storage temperature tstg -65 150 c note 2. all voltages with respect to ground. note 3. avss and dvss must be connected to the same ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (avss, dvss=0v; note 2) parameter symbol min typ max units power supplies: analog digital avdd dvdd 2.7 2.7 3.3 3.3 3.6 avdd v v note 2. all voltages with respect to ground. s/pdif receiver characteristics (ta=25 c; avdd, dvdd=2.7~3.6v) parameter symbol min typ max units input resistance zin - 10 - k ? input voltage vth 350 mvpp input sample frequency fs 32 - 192 khz dc characteristics (ta=25 c; avdd, dvdd=2.7~3.6v; unless otherwise specified) parameter symbol min typ max units power supply current normal operation (pdn= ?h?) (note 4) lp= ?0?, cm1-0= ?00? (note 5) lp= ?1?, cm1-0= ?00? (note 6) lp= ?1?, cm1-0= ?01? (note 7) power down (pdn = ?l?) (note 8) 14 7 2 10 28 14 - 100 ma ma ma a high-level input voltage low-level input voltage vih vil 70%dvdd dvss-0.3 - - dvdd+0.3 30%dvdd v v high-level output voltage (iout=-400 a) low-level output voltage (iout=400 a) voh vol dvdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a note 4. avdd=dvdd=3.3v. note 5. fs=192khz, x'tal=24.576mhz, pcks1-0= ?10? , c l =20pf. avdd=5ma (typ), dvdd=9ma (typ). note 6. fs=48khz, x'tal=24.576mhz, c l =20pf. avdd=4ma (typ), dvdd=3ma (typ). note 7. fs=48khz, x'tal=24.576mhz. the external load current is not included. note 8. rx inputs are open and all digital input pins are held at dvdd or dvss.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 6 - switching characteristics (ta=25 c; avdd, dvdd=2.7~3.6v; c l =20pf) parameter symbol min typ max units master clock timing crystal resonator frequency fxtal 11.2896 24.576 mhz external clock frequency duty cycle feclk declk 2.048 40 50 24.576 60 mhz % mcko output frequency duty cycle (note 9) fmck dmck 1.024 40 50 24.576 60 mhz % pll clock recover frequency (rx0, rx1) fpll 32 - 192 khz lrck timing frequency pll mode x?tal mode external clock mode duty cycle fs fs fs dlck 32 44.1 8 45 192 192 192 55 khz khz khz % audio interface timing bick frequency bick duty bick ? ? to lrck bick ? ? to sdto daux hold time daux setup time fbck dbck tmblr tbsd tdxh tdxs -20 20 20 64fs 50 20 15 hz % ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 50 50 150 50 50 45 70 ns ns ns ns ns ns ns ns ns ns reset timing pdn pulse width tpw 150 ns note 9. except the external clock input.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 7 - ? timing diagram 1/feclk teclkl vih teclkh xti vil declk = teclkh x feclk x 100 = teclkl x feclk x 100 1/fmck 50%dvdd mcko tmckl tmckh dmck = tmckh x fmck x 100 = tmckl x fmck x 100 1/fs lrck vih vil tlrl tlrh dlck = tlrh x fs x 100 = tlrl x fs x 100 figure 1. clock timing lrck bick sdto tbsd tmblr 50%dvdd 50%dvdd 50%dvdd daux tdxh tdxs vih vil figure 2. serial interface timing
asahi kasei [AK4117] ms0157-e-03 2004/04 - 8 - tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck figure 3. write/read command input timing tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil figure 4. write data input timing csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%dvdd vih vil vih vil vih vil figure 5. read data output timing 1
asahi kasei [AK4117] ms0157-e-03 2004/04 - 9 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%dvdd vih vil vih vil vih vil figure 6. read data input timing 2 tpw pdn vil figure 7. power down & reset timing
asahi kasei [AK4117] ms0157-e-03 2004/04 - 10 - operation overview ? non-pcm (ac-3, mpeg, etc.) and dts-cd bitstream detection the AK4117 has a non-pcm steam auto-detection function. when the 32-bit mode non-pcm preamble based on dolby ?ac-3 data stream in iec60958 interface? is detected, the npcm bit goes to ?1?. the 96-bit sync code consists of 0x0000, 0x0000, 0x0000, 0x0000, 0xf872 and 0x4e1f. detection of this pattern will set the npcm to ?1?. once the npcm is set to ?1?, it will remain ?1? until 4096 frames pass through the chip without an additional sync pattern being detected (timing diagram: figure 27 and figure 28). when those preambles are detected, the burst preambles pc (burst information: table 10) and pd (length code: table 11) that follow those sync codes are stored to registers. the AK4117 also has a dts-cd bitstream auto-detection function. when AK4117 detects dts-cd bitstreams, the dtscd bit goes to ?1?. if the next sync code does not occur within 4096 frames, the dtscd bit goes to ?0? until either the AK4117 detects the stream again. or?ed value of the npcm and dtscd bits are output to the auto bit. the AK4117 detects 14bit sync word of a dts-cd bitstream, while it does not detect 16bit sync word (0x7ffe8001). ? 192khz clock recovery the on-chip, low jitter pll has a wide lock range of 32khz to 192khz and a lock time of less than 20ms. the AK4117 has a sampling frequency detect function (32khz, 44.1khz, 48khz, 88.2khz, 96khz, 176. 4khz and 192khz) that uses either clock comparison against the x?tal oscillator or the channel status information. the pll loses lock when the received sync interval is incorrect. ? clock operation mode the AK4117 has two sources for mcko and sdto. 1) mcko and sdto source is recovered by pll from rx input. 2) mcko source is x?tal or external clock. sdto source is daux input. the cm1-0 bits select the clock operation mode (table 1). in mode 2, the clock source is switched from pll to x'tal when the pll loses lock. in mode3, even though the clock source is fixed to x'tal, the pll is also operating. this allows the monitoring of recovered data such as c bits. for mode2 and 3, it is recommended that the x?tal frequency and pll recovery frequency be set differently. mode cm1 cm0 unlck pll x'tal clock source sdto 0 0 0 - on on(note) pll rx default 1 0 1 - off on x'tal daux 0 on on pll rx 2 1 0 1 on on x'tal daux 3 1 1 - on on x'tal daux on: oscillation (power-up), off: stop (power-down) note : when the x?tal is not used as clock comparison for fs detection (i.e. xtl1,0= ?1,1?), the x?tal is off. table 1. clock operation mode select
asahi kasei [AK4117] ms0157-e-03 2004/04 - 11 - ? master clock output the AK4117 has a master clock output pin, mcko. in pll mode, pcks1-0 bits select the mcko frequency as shown in table 2. when mcko=512fs, mcko goes to ?l? when fs=96khz and 192khz. when mcko=256fs, mcko goes to ?l? when fs=192khz. when lp bit is set to ?1?, the AK4117 is in low power mode (default). in low power mode, pll lock range is up to 48khz and the mcko frequency is fixed to 256fs. in the x?tal mode, xcks1-0 bits select the ratio of the x?tal frequency to fs (sampling frequency). the div bit selects the ratio (x1 or x1/2) of the mcko frequency to the x?tal frequency (table 3). lp pcks1 pcks0 mcko fs [khz] 0 0 512fs 32 48 0 1 256fs 32 96 1 0 128fs 32 192 0 1 1 n/a n/a 1 x x 256fs 32 48 default table 2. master clock frequency select (pll mode: clock operation mode 0, 2(unlck=0)) fs [khz] mcko extclk [mhz] x?tal [mhz] xcks1 xcks0 x?tal or ext div=0 div=1 2.048 4.096 8.192 11.2896 12.288 24.576 0 0 128fs 128fs 64fs 16 32 64 88.2 96 192 0 1 256fs 256fs 128fs 8 16 32 44.1 48 96 default 1 0 512fs 512fs 256fs n/a 8 16 n/a n/a 48 1 1 1024fs 1024fs 512fs n/a n/a 8 n/a n/a n/a table 3. master clock frequency select (x?tal mode: clock operation mode 1, 2(unlck=1), 3)
asahi kasei [AK4117] ms0157-e-03 2004/04 - 12 - ? clock source the following circuits are available to feed a clock into the xti pin of AK4117. 1) x?tal mode the x?tal with proper value should be connected between xti and xto pins. xti xto a k4117 figure 8. x?tal mode (exck= ?0?) note: external capacitance depends on the crystal oscillator (typ.10-40pf). 2) external clock mode exck bit should be set to ?1? and the proper frequency cl ock input into the xti pin. xto pin should be left open. xti xto AK4117 external clock figure 9. external clock mode (exck= ?1?) 3) off mode cm1-0 bits should be set to ?00? and xtl1-0 bits to ?11? respectively. xti and xto pins should be left open. the xti pin can also be connected to ground externally. xti xto a k4117 figure 10. off mode (cm1-0= ?00?, xtl1-0= ?11?)
asahi kasei [AK4117] ms0157-e-03 2004/04 - 13 - ? sampling frequency and pre-emphasis detection the AK4117 has two methods for detecting the sample frequency: 1) clock comparison between recovered clock and the x?tal oscillator fs3-0 bits indicate the detected rx input frequency referr ed to x?tal frequency. xtl1-0 bits select the reference x?tal frequency (table 4). 2) sampling frequency information on channel status when xtl1-0= ?11?, fs3-0 bits indicate the decoded sampling frequency information from channel status. xtl1 xtl0 x?tal frequency 0 0 11.2896mhz default 0 1 12.288mhz 1 0 24.576mhz 1 1 (use channel status) table 4. reference x?tal frequency except xtl1-0= ?11? xtl1-0= ?11? register output fs consumer mode (note 2) professional mode fs3 fs2 fs1 fs0 clock comparison (note 1) byte3 bit3,2,1,0 byte0 bit7,6 byte4 bit6,5,4,3 0 0 0 0 44.1khz 44.1khz 3% 0 0 0 0 0 1 0 0 0 0 0 0 0 1 reserved reserved 0 0 0 1 (others) 0 0 1 0 48khz 48khz 3% 0 0 1 0 1 0 0 0 0 0 0 0 1 1 32khz 32khz 3% 0 0 1 1 1 1 0 0 0 0 1 0 0 0 88.2khz 88.2khz 3% ( 1 0 0 0 ) 0 0 1 0 1 0 1 0 1 0 96khz 96khz 3% ( 1 0 1 0 ) 0 0 0 0 1 0 1 1 0 0 176.4khz 176.4khz 3% ( 1 1 0 0 ) 0 0 1 0 1 1 1 1 1 0 192khz 192khz 3% ( 1 1 1 0 ) 0 0 0 0 1 1 note 1: at least 3% range is identified as the value in the table 5. in case of an intermediate frequency of these two, fs3-0 bits indicate the nearer value. when the frequenc y is much larger than 192khz or much smaller than 32khz, fs3-0 bits may indicate ?0001?. note 2: in consumer mode, byte3 bit3-0 are copied to fs3-0. table 5. sampling frequency information the pre-emphasis information is detected and reported on the pem bit. this information is extracted from channel 1 by default (cs12=0). it can be switched to channel 2 by changing the cs12 bit in the control register. consumer mode professional mode pem pre-emphasis byte 0 bits 3-5 byte 0 bits 2-4 0 off 0x100 110 1 on 0x100 110 table 6. pre-emphasis information
asahi kasei [AK4117] ms0157-e-03 2004/04 - 14 - ? system reset and power-down the AK4117 has a full power-down mode for all circuits th at is activated by the pdn pin, and a partial power-down mode activated by the pwn bit. the rstn bit initializes the internal registers and timing. the AK4117 should be reset once at power-up by bringing pdn pin = ?l?. pdn pin: all analog and digital circuits are placed in power-down and reset modes by bringing pdn= ?l?. all the registers are initialized and clocks are stopped. read/wr ite operations to the registers are disabled. rstn bit (address 00h; d0): all the registers except rstn, pwn, xtl1-0 and exck are initialized by bringing rstn bit = ?0?. the internal timings are also initialized. when rstn bit= ?0?, clocks are output, but sdto is ?l?. all register writes except rstn, pwn, xtl1-0 and exck are disabled . reading from the registers is enabled. pwn bit (address 00h; d1): clock recovery mode is initialized by bringing pwn bit = ?0?. clocks from the pll are stopped while the x?tal clocks continue to be output. unlike the pdn pin operation described above, internal registers and mode settings are not initialized. read/write operations to the registers are enabled. ? biphase input two receiver inputs (rx0 and rx1) are available. each input includes an amplifier for unbalance loads that can accept 350mvpp or greater signal. the ips bit selects the receiver channel (table 7). when the uoute bit = ?1?, the u bit (user data) can be output from the uout pin. ips input data 0 rx0 default 1 rx1 table 7. recovery data select uout lrck (except i 2 s) l0 r0 l1 r31 l31 l32 r191 sdto l191 r191 l30 l31 r30 l0 r190 lrck (i 2 s) figure 11. uout output timing
asahi kasei [AK4117] ms0157-e-03 2004/04 - 15 - ? biphase signal input circuit rx a k4117 0.1uf 75 ? coax 75 ? figure 12. consumer input circuit (coaxial input) note: when using a coaxial input, if the coupling level to this input from the next rx input line pattern exceeds 50mv, incorrect operation may occur. this can be reduced or prevented by adding a decoupling capacitor. rx a k4117 470 o/e optical receiver optical fiber 3.3v 3.3v figure 13. consumer input circuit (optical input; using 3.3v optical receiver)
asahi kasei [AK4117] ms0157-e-03 2004/04 - 16 - ? q-subcode buffers the AK4117 has a q-subcode buffer for cd application. the AK4117 takes q-subcode into registers under the following conditions: 1) the sync word (s0,s1) consists of at least 16 ?0?s. 2) the start bit is ?1?. 3) those 7-bits q-w follows to the start bit. 4) the distance between two start bits is 8-16 bits. the qint bit in the control register go es ?1? when the new q-subcode differs from old one, and goes ?0? when qint bit is read. 1 2 3 4 5 6 7 8 * s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : s97 1 q97 r97 s97 t97 u97 v97 w97 0? s0 0 0 0 0 0 0 0 0 0? s1 0 0 0 0 0 0 0 0 0? s2 1 q2 r2 s2 t2 u2 v2 w2 0? s3 1 q3 r3 s3 t3 u3 v3 w3 0? : : : : : : : : : : (*) number of "0" : min=0; max=8. figure 14. configuration of u-bit(cd) q2 q3 q4 q5 q6 q7 q8 q9 q10 q11 q12 q13 q14 q15 q16 q17 q18 q19 q20 q21 q22 q23 q24 q25 ctrl adrs track number index q26 q27 q28 q29 q30 q31 q32 q33 q34 q35 q36 q37 q38 q39 q40 q41 q42 q43 q44 q45 q46 q47 q48 q49 minute second frame q50 q51 q52 q53 q54 q55 q56 q57 q58 q59 q60 q61 q62 q63 q64 q65 q66 q67 q68 q69 q70 q71 q72 q73 zero absolute minute absolute second q74 q75 q76 q77 q78 q79 q80 q81 q82 q83 q84 q85 q86 q87 q88 q89 q90 q91 q92 q93 q94 q95 q96 q97 absolute frame crc g(x)=x 16 +x 12 +x 5 +1 figure 15. q-subcode addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h q-subcode address / control q9 q8 q3 q2 12h q-subcode track q17 q16 q11 q10 13h q-subcode index 14h q-subcode minute 15h q-subcode second 16h q-subcode frame 17h q-subcode zero 18h q-subcode abs minute 19h q-subcode abs second 1ah q-subcode abs frame q81 q80 q75 q74 figure 16. q-subcode register map q
asahi kasei [AK4117] ms0157-e-03 2004/04 - 17 - ? interrupt handling there are eight events which caus e the int1-0 pins to go ?h?. 1. unlck: pll unlock state detect ?1? when the pll loses lock. th e AK4117 loses lock when the di stance between two preambles is not correct or when those preambles are not correct. 2. par: parity error or biphase coding error detection ?1? when parity error or biphase coding error is detected, updated every sub-frame cycle. reading this register resets it. 3. auto: non-pcm or dts-cd bit stream detection the or function of npcm and dtscd bits is output to the auto bit. 4. v: validity flag detection ?1? when validity flag is detected. updated every sub-frame cycle. 5. audion: non-audio detection ?1? when the ?audio? bit in recovered channel status indicates ?1?. updated every block cycle. 6. stc: sampling frequency or pre-emphasis information change detection ?1? when fs3-0 or pem bit changes. reading this register resets it. 7. qint: u bit (q-subcode) sync flag ?1? when the q-subcode differs from old one, and stays ?1? until this register is read. updated every sync code cycle for q-subcode. reading this register resets it. 8. cint: channel status sync flag ?1? when received c bits differ from old ones, and stays ?1? until this register is read. updated every block cycle. reading this register resets it. int1-0 pins output an or?ed signal based on the above eight interrupt events. when masked, the interrupt event does not affect the operation of the int1-0 pins (the masks do not affect the resisters (unlck, par, etc.) themselves). once int0 pin goes to ?h?, it maintains ?h? for 1024 cycles (this value can be changed by the efh1-0 bits) after all events not masked by mask bits are cleared. int1 pin immedi ately goes to ?l? when those events are cleared. unlck, auto, v and audion bits indicate the interrupt status events above in real time. once par, stc, qint or cint bit goes to ?1?, it stays ?1? until the register is read. int pin holds ?h? for one sub-frame, then goes to ?l? in this case. when the AK4117 loses lock, the channel status bits are initiali zed. in this initial state, int0 outputs the or?ed signal between unlck and par bits. int1 outputs the or?ed sign al to auto, v and audion. int1-0 pins are ?l? when the pll is off (clock operation mode 1). event unlck par others sdto pin 1 x x ?l? 0 1 x previous data 0 0 x output table 8. interrupt handling
asahi kasei [AK4117] ms0157-e-03 2004/04 - 18 - interrupt (unlck, par,..) int1 pin sdto (unlck) mcko,bick,lrck (unlck) previous data register (par,stc, cint,qint) hold ?1? command read 05h mcko,bick,lrck (except unlck) (fs: around 20khz) sdto (par error) hold time = 0 reset (interrupt) sdto (others) normal operation int0 pin hold time (max: 4096/fs) register (others) free run figure 17. int1-0 pin timing
asahi kasei [AK4117] ms0157-e-03 2004/04 - 19 - int0/1 pin ="h" no yes yes initialize pdn pin ="l" to "h" read 05h mute dac output read 05h no (each error handling) read 05h (resets registers) int0/1 pin ="h" release muting figure 18. interrupt handling sequence example 1
asahi kasei [AK4117] ms0157-e-03 2004/04 - 20 - int1 pin ="h" no yes initialize pdn pin ="l" to "h" read 05h read 05h and detect qsub= ?1? no (read q-buffer) new data is valid int1 pin ="l" qcrc = ?0? yes yes new data is invalid no figure 19. interrupt handling sequence example (for q/cint)
asahi kasei [AK4117] ms0157-e-03 2004/04 - 21 - ? audio serial interface format the dif2-0 bits can select six serial data formats as shown in table 9. in all formats, the serial data is msb-first, 2?s compliment format. the sdto is clocked out on the falling edge of bick and the daux is latched on the rising edge of bick. bick outputs 64fs clock. when the sdto format is equal or less than 20 bits (mode 0-2), lsbs in the sub-frame are truncated. in modes 3-7, the last four lsbs are auxiliary data (see figure 20). when a parity error, biphase error or frame length error occurs in a sub-frame, the AK4117 continues to output the last normal sub-frame data from sdto repeatedly until the error is removed. when an unlock error occurs, the AK4117 outputs ?0? from sdto. when using the daux pin, the data is transformed and output from sdto. the daux pin is used in clock operation modes 1, 3 and in the unlock stat e of mode 2. the input data format to daux should be left-justified except in mode 5. in mode 5, both the input data format of daux and the output data format of sdto are i 2 s. 0 3 4 7 8 11 12 27 28 29 30 31 preamble aux. lsb msb vuc p sub-frame of iec60958 0 23 AK4117 audio data (msb first) lsb msb figure 20. bit configuration mode dif2 dif1 dif0 daux sdto lrck 0 0 0 0 24bit, left justified 16bit, right justified h/l 1 0 0 1 24bit, left justified 18bit, right justified h/l 2 0 1 0 24bit, left justified 20bit, right justified h/l 3 0 1 1 24bit, left justified 24bit, right justified h/l 4 1 0 0 24bit, left justified 24bit, left justified h/l default 5 1 0 1 24bit, i 2 s 24bit, i 2 s l/h 6 1 1 0 7 1 1 1 reserved table 9. audio data format
asahi kasei [AK4117] ms0157-e-03 2004/04 - 22 - lrck bick (64fs) sdto 0 1 2 31 0 1 15:msb, 0:lsb lch data rch data 15 17 16 15 31 0 1 2 17 16 01 0 1 15 14 14 15 figure 21. mode 0 timing lrck bick (64fs) sdto 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 9 11 10 9 31 0 1 2 11 10 01 0 1 12 21 20 20 21 12 22 23 22 23 figure 22. mode 3 timing lrck bick (64fs) sdto 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 21 23 22 21 31 0 1 2 23 22 23 22 2 24 1 0 0 1 24 21 22 23 32 23 22 figure 23. mode 4 timing lrck bick (64fs) sdto 0 1 2 31 0 1 23:msb, 0:lsb lch data rch data 23 22 21 31 0 1 2 23 22 23 22 24 1 0 24 32 23 25 2 0 1 21 22 23 25 figure 24. mode 5 timing
asahi kasei [AK4117] ms0157-e-03 2004/04 - 23 - ? serial control interface the internal registers may be either written or read by the 4-wire p interface pins: csn, cclk, cdti & cdto. the data on this interface consists of chip address (2bits, c1-0 are fixed to ?00?), read/write (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operations, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the maximum speed of cclk is 5mhz. pdn= ?l? resets the registers to their default values. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a 1 a 2 a 3 a 4 r/w c0 a 0d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a 1 a 2 a3 a 4 r/w c0 a 0d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1,c0: chip address (fixed to ?00?) r/w: read/write (0:read, 1:write) a4-a0: register address d7-d0: control data figure 25. 4-wire serial control i/f timing
asahi kasei [AK4117] ms0157-e-03 2004/04 - 24 - ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 exck xtl1 xtl0 pwn rstn 01h clock control lp pcks1 pcks0 div xcks1 xcks0 cm1 cm0 02h input/output control ips uoute cs12 efh1 efh0 dif2 dif1 dif0 03h int0 mask mulk0 mpar0 maut0 mv0 maud0 mstc0 mcit0 mqit0 04h int1 mask mulk1 mpar1 maut1 mv1 maud1 mstc1 mcit1 mqit1 05h receiver status 0 unlck par auto v audion stc cint qint 06h receiver status 1 0 dtscd npcm pem fs3 fs2 fs1 fs0 07h receiver status 2 0 0 0 0 0 0 ccrc qcrc 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 0dh burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0eh burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 0fh burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 10h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 11h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 12h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 13h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 14h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 15h q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 16h q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 17h q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 18h q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 19h q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1ah q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 note: when pdn pin goes to ?l?, the registers are initialized to their default values. when rstn bit goes to ?0?, the internal timing is reset and all registers except rstn, pwn, xtl1-0 and exck bits are initialized to their default values. all data can be written to the registers even if pwn bit is ?0?.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 25 - ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 exck xtl1 xtl0 pwn rstn r/w rd rd rd r/w r/w r/w r/w r/w default 0 0 0 0 0 0 1 1 rstn: timing reset & register initialize 0: reset & initialize (except rstn, pwn, xtl1-0 and exck bits) 1: normal operation (default) pwn: power-down for clock recovery part 0: power down 1: normal operation (default) xtl1-0: reference x?tal frequency select (table 4; default: 00) exck: external clock mode select 0: x?tal mode (default) 1: external clock mode (feedback resistor of x?tal oscillator circuit is open.) addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h clock control lp pcks1 pcks0 div xcks1 xcks0 cm1 cm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 1 0 0 1 0 0 cm1-0: master clock operation mode select (table 1; default: 00) xcks1-0: master clock fre quency select at x?tal mode (table 3; default: 01) div: master clock output select at x?tal mode 0: same frequency as x?tal (default) 1: half frequency of x?tal pcks1-0: master clock frequency select at pll mode (table 2; default: 01) lp: low power mode select (table 2) 0: normal mode 1: low power mode (default) in low power mode, fs cannot exceed 48khz.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 26 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h format control ips uoute cs12 efh1 efh0 dif2 dif1 dif0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 0 0 1 1 0 0 dif2-0: audio data format control (table 9; default: 100) efh1-0: int0 pin hold count select 00: 512 lrck 01: 1024 lrck (default) 10: 2048 lrck 11: 4096 lrck cs12: channel status select 0: channel 1 (default) 1: channel 2 this bit selects which channel status is used to derive c-bit buffers, audion, pem, fs3-0, pc, pd and crc. uoute: u-bit output enable 0: disable (default) 1: enable. u-bit is output from uout pin. ips: input recovery data select (table 7) 0: rx0 (default) 1: rx1
asahi kasei [AK4117] ms0157-e-03 2004/04 - 27 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h int0 mask mulk0 mpar0 maut0 mv0 maud0 mstc0 mcit0 mqit0 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 0 0 1 1 1 1 1 1 mqit0: mask enable for qint bit mcit0: mask enable for cint bit mstc0: mask enable for stc bit maud0: mask enable for audion bit mv0: mask enable for v bit maut0: mask enable for auto bit mpar0: mask enable for par bit mulk0: mask enable for unlock bit 0: mask disable 1: mask enable the factor which mask bit is set to ?0? affects int0 pin operation. addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h int0 mask mulk1 mpar1 maut1 mv1 maud1 mstc1 mcit1 mqit1 r/w r/w r/w r/w r/w r/w r/w r/w r/w default 1 1 0 0 0 1 1 1 mqit1: mask enable for qint bit mcit1: mask enable for cint bit mstc1: mask enable for stc bit maud1: mask enable for audion bit mv1: mask enable for v bit maut1: mask enable for auto bit mpar1: mask enable for par bit mulk1: mask enable for unlock bit 0: mask disable 1: mask enable the factor whose mask bit is set to ?0? affects int1 pin operation.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 28 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 05h receiver status 0 unlck par auto v audion stc cint qint r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 qint: q-subcode buffer interrupt 0: no change 1: changed this bit goes to ?1? when q-subcode stored in register addresses 11h to 1ah is updated. cint: channel status buffer interrupt 0: no change 1: changed this bit goes to ?1? when c-bit stored in register addresses 08h to 0ch changes. stc: sampling frequency or pre-emphasis information change detection 0: no detect 1: detect this bit goes to ?1? when either the fs3-0 or pem bit changes. audion: audio bit output 0: audio 1: non audio this bit is made by enc oding channel status bits. v: validity bit 0: valid 1: invalid auto: non-pcm or dts-cd bit steam auto detection 0: no detect 1: detect this bit outputs the or?ed value of npcm and dtscd bits. par: parity error or biphase error status 0:no error 1:error this bit goes to ?1? if a parity error or biphase error is detected in the sub-frame. unlck: pll lock status 0: lock 1: unlock qint, cint, stc and par bits are initialized when 05h is read.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 29 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h receiver status 1 0 dtscd npcm pem fs3 fs2 fs1 fs0 r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 1 fs3-0: sampling frequency detection (table 5) pem: pre-emphasis detect 0: off 1: on this bit is made by encodi ng the channel status bits. npcm: non-pcm bit stream auto detection 0: no detect 1: detect dtscd: dts-cd bit stream auto detect 0: no detect 1: detect addr register name d7 d6 d5 d4 d3 d2 d1 d0 07h receiver status 2 0 0 0 0 0 0 ccrc qcrc r/w rd rd rd rd rd rd rd rd default 0 0 0 0 0 0 0 0 qcrc: cyclic redundancy check for q-subcode 0: no error 1: error ccrc: cyclic redundancy check for channel status 0: no error 1: error this bit is enabled only in professional mode and only for the channel selected by the cs12 bit.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 30 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 08h rx channel status byte 0 cr7 cr6 cr5 cr4 cr3 cr2 cr1 cr0 09h rx channel status byte 1 cr15 cr14 cr13 cr12 cr11 cr10 cr9 cr8 0ah rx channel status byte 2 cr23 cr22 cr21 cr20 cr19 cr18 cr17 cr16 0bh rx channel status byte 3 cr31 cr30 cr29 cr28 cr27 cr26 cr25 cr24 0ch rx channel status byte 4 cr39 cr38 cr37 cr36 cr35 cr34 cr33 cr32 r/w rd default not initialized cr39-0: receiver channel status byte 4-0 all 40 bits are updated at the same time every block (192 frames) cycle. addr register name d7 d6 d5 d4 d3 d2 d1 d0 0dh burst preamble pc byte 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 0eh burst preamble pc byte 1 pc15 pc14 pc13 pc12 pc11 pc10 pc9 pc8 0fh burst preamble pd byte 0 pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 10h burst preamble pd byte 1 pd15 pd14 pd13 pd12 pd11 pd10 pd9 pd8 r/w rd default not initialized pc15-0: burst preamble pc byte 0 and 1 pd15-0: burst preamble pd byte 0 and 1 addr register name d7 d6 d5 d4 d3 d2 d1 d0 11h q-subcode address / control q9 q8 q7 q6 q5 q4 q3 q2 12h q-subcode track q17 q16 q15 q14 q13 q12 q11 q10 13h q-subcode index q25 q24 q23 q22 q21 q20 q19 q18 14h q-subcode minute q33 q32 q31 q30 q29 q28 q27 q26 15h q-subcode second q41 q40 q39 q38 q37 q36 q35 q34 16h q-subcode frame q49 q48 q47 q46 q45 q44 q43 q42 17h q-subcode zero q57 q56 q55 q54 q53 q52 q51 q50 18h q-subcode abs minute q65 q64 q63 q62 q61 q60 q59 q58 19h q-subcode abs second q73 q72 q71 q70 q69 q68 q67 q66 1ah q-subcode abs frame q81 q80 q79 q78 q77 q76 q75 q74 r/w rd default not initialized q2-81: q-subcode (figure 14 and figure 15) all 80 bits are updated at the same time every sync code cycle for q-subcode.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 31 - ? burst preambles in non-pcm bitstreams 0 16 bits of bitstream 34 7 811 12 27 28 29 30 31 preamble aux. lsb msb v u c p sub-frame of iec60958 015 pa pb pc pd burst_payload stuffing repetition time of the burst figure 26. data structure in iec60958 preamble word length of field contents value pa 16 bits sync word 1 0xf872 pb 16 bits sync word 2 0x4e1f pc 16 bits burst info see table 11 pd 16 bits length code numbers of bits table 10. burst preamble words
asahi kasei [AK4117] ms0157-e-03 2004/04 - 32 - bits of pc value contents repetition time of burst in iec958 frames 0-4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16-31 data type null data dolby ac-3 data reserved pa use mpeg-1 layer1 data mpeg-1 layer2 or 3 data or mpeg-2 without extension mpeg-2 data with extension mpeg-2 aac adts mpeg-2, layer1 low sample rate mpeg-2, layer2 or 3 low sample rate reserved dts type i dts type ii dts type iii atr a c atrac2/3 reserved 4096 1536 384 1152 1152 1024 384 1152 512 1024 2048 512 1024 5, 6 0 reserved, shall be set to ?0? 7 0 1 error-flag indicating a valid burst_payload error-flag indicating that the burst_payload may contain errors 8-12 data type dependent info 13-15 0 bit stream number, shall be set to ?0? table 11. fields of burst info pc
asahi kasei [AK4117] ms0157-e-03 2004/04 - 33 - ? non-pcm bitstream timing 1) when non-pcm preamble does not arrive within 4096 frames, pa pc 1 pd 1 pb pa pc 2 pd 2 pb pa pc 3 pd 3 pb ?0? pc 1 pc 2 ?0? pd 1 pd 2 pd 3 pc 3 pdn pin bit stream a uto bit pc register pd registe r repetition time >4096 frames figure 27. timing example 1 2) when non-pcm bitstream stops (when mulk0=0), pa pc 1 pd 1 pb stop pa pc n pd n pb pc 0 pc 1 pd 0 pd 1 pd n pc n int0 pin bit stream a uto bi t pc register pd registe r int0 hold time 2~3 syncs (b,m or w) <20ms (lock time) asahi kasei [AK4117] ms0157-e-03 2004/04 - 34 - system design figure 29 is a system connection diagram. an evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. r 1 a vdd 2 rx1 3 nc 4 rx0 5 dvdd 6 dvs s 7 xti 8 xt o 9 lrck 10 bick 11 sdt o 12 a vs s 24 pd n 23 int 0 22 int1 21 c s n 20 ccl k 19 cdti 18 cdt o 17 uou t 16 n c 15 mck o 14 dau x 10u + AK4117 3.3v supply 0.1u 10u + 12 k s/pdif (see figure 12-14) ad/da micro- controller c 0.1u 3.3v supply c (see figure 8-10 ) 13 dsp (shield) figure 29. typical connection diagram notes: (1) ?c? depends on the x?tal. (typ.10-40pf) (2) avss and dvss must be connected the same ground plane.
asahi kasei [AK4117] ms0157-e-03 2004/04 - 35 - package 0.1 0.1 0-10 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.15 0.1 0.65 *7.8 0.15 1.25 0.2 a 1 12 13 24 24 p in vsop ( unit: mm ) 7.6 0.2 0.5 0.2 *5.6 0.2 ? material & lead finish package molding compound: epoxy lead frame material: cu lead frame surface treatmen t: solder (pb free) plate
asahi kasei [AK4117] ms0157-e-03 2004/04 - 36 - marking a km a k4117vf a axxxx contents of aaxxxx aa: lot# xxxx: date code important notice ? these products and their specifications are subject to change without notice. before considering any use or application, consult the asahi kasei microsystems co., ltd. (akm) sales office or authorized distributor concerning their current status. ? akm assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. ? any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. ? akm products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and akm assumes no responsibility relating to any such use, except with the express written consent of the representative director of akm. as used here: (a) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. ? it is the responsibility of the buyer or distributor of an akm product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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